Three-dimensional ferroelectric random-access memory (feram)

ABSTRACT

A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low- cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part of U.S. pat.application (“Parent Application I”), serial no. 17/039,746, entitled“THREE-DIMENSIONAL FERROELECTRIC RANDOM-ACCESS MEMORY (FERAM),” filed onSep. 30, 2020, which is a divisional application of U.S. pat.application ("Parent Application II), serial no. 16/733,102, entitled“Three-Dimensional Ferroelectric Random-Access Memory (FeRAM),” filed onJan. 2, 2020, which is a continuation-in-part application of U.S. pat.application (“Parent Application III”), serial no. 16/558,072, entitled“Three-Dimensional Ferroelectric Random-Access Memory (FeRAM),” filed onAug. 31, 2019, which is related to and claims priority of U.S.provisional patent application (“Provisional Application”), serial no.62/846,418, entitled “3D Ferroelectric Random-Access Memory With MLCCapability,” filed on May 10, 2019.

The disclosures of Parent Application I, Parent Application II, ParentApplication III and Provisional Application are hereby incorporated byreference in their entireties.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to memory circuits. In particular, thepresent invention relates to high-density, ferroelectric random-accessmemory arrays including memory cells provided in a 3-dimensionalconfiguration.

2. Discussion of the Related Art

An erase operation in a 3-dimensional non-volatile memory circuits(e.g., NAND-type flash memory circuits) is typically carried out on ablock-by-block basis, which involves a long access time. Such memorycircuits are not suitable for use in high speed (~50 ns), high densitystorage class memory (SCM) applications.

Other alternative memory circuits, for example, include:

-   (i) 3D XPoint memory circuits, jointly developed by Intel    Corporation and Micron Corporation, while allowing bit-by-bit access    that is suitable for SCM applications, use cross-point patterning    (i.e., double exposures for patterning each material layer), which    is prohibitively high in manufacturing cost. Also, such 3D XPoint    memory circuits are based on a phase-change material (PCM), which    results in high leakage currents and, hence, high power dissipation    from sneak paths. Selector devices are needed to reduce the leakage    currents from sneak paths, which increase the complexity of process    and device integration.-   (ii) U.S. Patents 10,249,370, 10,121,554, 10,121,553, and 9,892,800    disclose 3-dimensional vertical NOR-type memory string arrays, which    require complicated X and Y patterning schemes. Due to NOR    architecture, the power consumption is also high.

Ferroelectric memory circuits provide yet another alternative. U.S.Patent 6,067,244 to T. Ma, entitled "Erroelectric Dynamic Random AccessMemory, filed on Sep. 16, 1998, discloses a ferroelectric field-effecttransistor (FeFET) that can serve as a memory circuit, as dipole momentsin the FeFET can be aligned in either one of two configurations by anelectric field. However, conventional ferroelectric materials, such asthose based on lead zirconate titanate (PZT) and strontium bismuthtantalate (SBT), for example, do not provide high-density memorycircuits. This is because the ferroelectric layer in an FeFET based onthese materials must at least 70 nm thick.

FeFETs based on Hafnium oxide (HfO₂) are, however, promising. U.S.patent application publication 2018/0366547A1('“Liu”) discloses variousexamples of FeFETs. For example, FIGS. 2 a and 2 b , reproducedrespectively from FIG. 4A and FIG. 4B in Liu’s disclosure, illustratethe programmed states of exemplary FeFET 1.

As shown in both FIGS. 2 a and 2 b , FeFET 1is formed on ap⁻-typesubstrate 10 and includes n⁺-type source and drain regions 101and 102, respectively, channel region 103, tunneling dielectric layer13, charge storage region 12 and gate electrode 11. Charge region 12includes ferroelectric layer 120 and paraelectric layer 121.Paraelectric layer 121 has a "quantum well'' energy band structure,which enables a charge-trapping capability suitable for a data storageapplication. Paraelectric layer 121 may have, for example, alternatinglayers of a base material and a dielectric material. The base materialmay be, for example, Hf_(j) _(-x) Si_(x)O₂-- x being a value between0.02 and 0.65, while the dielectric material may be selected from thegroup consisting of hafnium oxide, zirconium oxide, titanium oxide,titanium nitride, tantalum nitride, aluminum oxide, tantalum oxide andany combination thereof. The alternating layers of base and dielectricmaterials may be formed using, for example, ALD processes.

Ferroelectric layer 120 may include an alkaline earth metal oxide or atransition metal oxide, such as hafnium oxide, zirconium oxide orhafnium zirconium oxide, with or without a 2-10%dopant selected from thegroup consisting of silicon, aluminum, yttrium, strontium, gadolinium,lanthanum and any combination thereof. One example of a ferroelectricmaterial is Hf_(1-x)Si_(x)O_(2,) x ranging between 0.01 and 0.05. Thecomposite material may also include hydrogen atoms in the manufacturingprocess. Liu discloses that the charge storage region 12 may be 1.0-30.0nm thick, preferably 5.0~15.0 nm thick.

As shown in FIG. 2 a , when a positive bias (e.g., Vt) is applied togate electrode 11,the electric dipoles in the ferroelectric layer 12align with the electric field, such that electrons in channel region 103tunnel through tunnel dielectric layer 13 into and are trapped inparaelectric layer 121. The trapped charge causes positive chargecarriers (i.e., holes) to accumulate in channel region 103 (“0” state,which provides a polarization switching voltage for the storagetransistor). In this “0” state. FeFET 1 is non-conducting at the readvoltage.

As shown in FIG. 2 b , when a negative bias (e.g., -Vt) is applied togate electrode 11, the electric dipoles in charge storage region 12allow holes in channel region 103 to tunnel to and be trapped inparaelectric layer 121. The trapped charge cause electron accumulationat channel region 103 (“1” state, which provides a negative polarizationswitching voltage). In this “1” state, FeFET 1 conducting at the readvoltage.

Liu also discloses that the ferroelectric layer 120 and paraelectriclayer 121 need not be distinct. The ferroelectric layer 120 andparaelectric layer 121 may be provided as a single layer as a blend ofthe ferroelectric and paraelectric materials.

As disclosure in Liu, a hafnium oxide-based FeFET may be made with aferroelectric layer that is less than 10 nm thick. Furthermore, such anFeFET may provide a 1-volt threshold-shift window. For example, thearticle, entitled “Low-Leakage-Current DRAM-Like Memory Using aOne-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric”(“Cheng”), by C. Cheng and A. Chin, published in IEEE Electronic DeviceLetters, vol. 35, No. 1, 2014, pp. 138-140, disclose a high-enduranceFeFET with a 30 nm thick zirconium-doped HfO₂ ferroelectric layer thatcan be programmed or erase in 5 ns.

FIG. 1 a shows an architecture of an AND-type FeFET array that can belaid out in a conventional 4F² configuration. FIG. 1 a also provides atable that shows the voltage biases for the word line (WL(m), the sourceline (SL(m)) and the bit line (BL(m)) of a selected FeFET, as well asthe voltage biases for the word line (WL(m+1), the source line (SL(m+1))and the bit line (BL(m+1)) of a non-selected FeFET, during program,erase and read operations. In Cheng, for example, the programmingvoltage V_(pmg) and the read voltage V_(read) for such an FeFET may be-4.0 volts and -0.1 volts, respectively.

FIG. 1 b shows an architecture of a NOR-type FeFET array. FIG. 1 b alsoprovides a table that shows the voltage biases for the word line (WL(m),the source line (SL(m)) and the bit line (BL(m)) of a selected FeFET, aswell as the voltage biases for the word line (WL(m+1), the source line(SL(m+1)) and the bit line (BL(m+1)) of a non-selected FeFET, duringprogram, erase and read operations.

SUMMARY

The present invention provides a 3-dimensional vertical memory stringarray that includes high-speed ferroelectric field-effect transistor(FET) cells that are low- cost, low-power, or high-density and suitablefor SCM applications. The memory circuits of the present inventionprovide random-access capabilities.

According to one embodiment of the present invention, a memory stringformed above a planar surface of substrate includes: (a) a vertical gateelectrode (e.g., tungsten or a heavily doped semiconductor) extendinglengthwise along a vertical direction relative to the planar surface,(b) a ferroelectric layer provided over at least a portion of the gateelectrode along a horizontal direction substantially parallel the planarsurface and extending lengthwise along the vertical direction; (c) agate oxide layer provided over at least a portion of the ferroelectriclayer along the horizontal direction and extending lengthwise along thevertical direction; (d) a channel layer provided over at least a portionof the gate oxide layer along the horizontal direction and extendinglengthwise along the vertical direction; and conductive semiconductorregions embedded in and isolated from each other by an oxide layerarrayed along the horizontal direction, wherein the gate electrode, theferroelectric layer, the channel layer, the gate oxide layer and eachadjacent pair of semiconductor regions from a storage transistor of thememory string, and wherein the adjacent pair of semiconductor regionsserve as source and drain regions of the storage transistor. Inaddition, a barrier layer (e.g., titanium nitride, tungsten nitride ortantalum nitride) may be provided between the gate electrode and theferroelectric layer. The drain or source region may also be provideddrain or source electrodes (e.g., tungsten or n⁺ polysilicon).

The memory strings of the present invention may be organized into amemory array, and a staircase configuration provides electrical contactsto each of the source or drain electrodes. Storage transistors may beprovided on opposite sides of each memory hole in which the gate, theferroelectric layer, the gate oxide layer and the channel silicon layerare provided. One or more networks of global word line conductors eachconnecting the gate electrodes of a selected group of the memory stringsmay be provided above the memory array, below the memory array or both.

The ferroelectric layer comprises a zirconium-doped or silicon-dopedHfO₂ ferroelectric material. The zirconium-doped hafnium silicon oxidemay have a zirconium content of 40-60%, preferably 45-55%. Thesilicon-doped hafnium silicon oxide may have a silicon content of2.0-5.0%, preferably 2.5-4.5%. The hafnium silicon oxide is prepared bydepositing HfO₂ and SiO₂ or ZrO₂ using an ALD layer-by-layer laminationstep.

In one embodiment the memory string further includes a charge-trappinglayer that is between the gate oxide layer and the ferroelectric layeror between the ferroelectric layer and the barrier layer.

In one embodiment, the channel layer and the conductive semiconductorregions are provided by doped silicon carbide (SiC) materials, formedusing chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Various manufacturing processes, some of which are illustrated herein,may be used to fabricate a memory array of the memory strings of thepresent invention.

The present invention is better understood upon consideration of thedetailed description below in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a shows an architecture of an AND-type FeFET array that can belaid out in a conventional 4F² configuration.

FIG. 1 b shows an architecture of a NOR-type FeFET array.

FIGS. 2 a and 2 b , reproduced from FIGS. 4A and 4B of U.S. pat.application publication 2018/0366547A1 (“Liu’’), illustrate theprogrammed states of exemplary FeFET 1.

FIG. 3 a shows a vertical section of memory array 300, which includes aregular arrangement of vertical 3-dimensional (3-D) FeFET strings; FIG.3 a shows, in particular, vertical 3-D FeFET strings 300 a, 300 b and300 c, according to one embodiment of the present invention.

FIG. 3 b shows an Y-Z plane cross section of memory array 300, showingthe gate, drain and source connectivity’s of eight vertical 3-D FeFETstrings, according to one embodiment of the present invention.

FIGS. 4 a, 4 b, 4 c, 4 d(i), 4 d(ii),4 e, 4 f, 4 g, 4 h(i), 4 h(ii), 4i(i), 4 i(ii), 4 j(i), 4 j(ii), 4 k(i), 4 k(ii), 41(i), and 41(ii)illustrate an exemplary fabrication process for memory array 400, inaccordance with one embodiment of the present invention.

FIG. 5 shows memory array 400 provided electrical contacts orconnections to drain or source electrodes 423 via staircase structureson both sides of memory array 400 and contacts or connections to gateelectrodes 423 using the bottom global word lines (e.g., global wordline 401).

FIGS. 6 a, 6 b, 6 c(i), 6 c(ii), 6 d, 6 e, 6 f(i), 6 f(ii), 6 g(i), 6g(ii), 6 h(i), 6 h(ii), 6 i, and 6 j illustrate an exemplary fabricationprocess for memory array 600, in accordance with one embodiment of thepresent invention.

FIGS. 7 a, 7 b(i), 7 b(ii), 7 c(i), 7 c(ii), 7 d, 7 e, 7 f, and 7 gillustrate an exemplary fabrication process for memory array 700, inaccordance with one embodiment of the present invention.

FIGS. 8 a, 8 b-1, 8 b-2, 8 c, 8 d-1, 8 d-2, 8 e, 8 f, 8 g(i), 8 g(ii), 8h(i), 8 h(ii), 8 i(i), 8 i(ii), 8 i(iii) and 8 j illustrate an exemplaryfabrication process for memory array 800, in accordance with oneembodiment of the present invention.

To facilitate cross-referencing among the figures, like elements areassigned like reference numerals. The figures may depict 3-dimensionalobjects from different perspectives. To facilitate description of3-dimensional objects, a cartesian coordinate system is provided, withX- and Y-directions denoting orthogonal horizontal directions and theZ-direction denoting the vertical direction. As this detaileddescription refers to structures fabricated on a planar surface of asubstrate, “vertical” is understood to refer to the directionsubstantially perpendicular to the planar surface and “horizontal” isunderstood to refer to directions substantially parallel to the planarsurface.

DETAIELD DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention may be carried out by, for example, a verticalmetal-ferroelectric-insulator semiconductor (MFIS) transistor thatincludes (a) tungsten/titanium nitride or n⁺ polysilicon/titaniumnitride gate electrode, (ii) zirconium-doped or silicon-doped HfO₂ferroelectric layer, (iii) a gate oxide layer, (iv) a p-type channelregion, (v) an n-type source region, and (v) an n-type drain region.

In such an MFIS transistor, n⁺ polysilicon in the gate electrode may bearsenic-doped polysilicon with dopant concentration of 5.0 × 10²¹ to 1.0× 10²² cm⁻³. The HfO₂ ferroelectric layer may be 5.0-15.0 nm thick,preferably 8.0-12.0 nm thick, deposited by ALD. If doped by zirconium,the ferroelectric layer should have zirconium content of 40-60%,preferably 45-55%. If doped by silicon, the ferroelectric layer shouldhave silicon content of 2.0-5.0%, preferably 2.5-4.5%. The gate oxidelayer may be, for example, 1.0-3.0 nm thick silicon oxide (SiO₂) orsilicon oxynitride (SiON). The p-type channel region may be, forexample, intrinsic polysilicon or boron-doped polysilicon with a dopantconcentration of 1.0 × 10¹⁶ to 1.0 × 10¹⁸ cm⁻³, deposited by CVD, usingany of boron, diborane (H₂B₂), and trimethyl borane (B(CH₃)₃ gases, orany of their combinations). The n-type drain and source regions may eachbe, for example, phosphorus-doped or arsenic-doped polysilicon with adopant concentration of 1.0 x 10²⁰ to 1.0 × 10²² cm⁻³ , deposited byCVD, using phosphine (PH₃) or phosphorus trichloride (PC1₃), ifphosphorus-doped, and arsenic or arsenic hydride (AsH3), ifarsenic-doped.

Alternatively, in some embodiments, the p-type channel region may be,for example, boron-doped or aluminum-doped SiC with a dopantconcentration of 1.0 × 10¹⁵ to 1.0 × 10¹⁸ cm⁻³, deposited by ALD or CVD.SiC may be deposited using an ALD process, at a temperature between 590°C. -675° C., using acetylene (C₂H₂) or ethylene (C₂H₄), as a carbonprecursor, and silicon chloride (Si₂Cl₂) or silicon hydride (Si₂H₆) as asilicon precursor. The n-type drain region and the n-type source regionmay be similarly provided by ALD nitrogen-doped or phosphorus-doped SiC,with a dopant concentration of 1.0 × 10¹⁹ to 1.0 × 10²² cm⁻³.

Si-doped Hf_(1-x)Si_(x)O_(y) ferroelectric thin-film may be formed bydepositing HfO₂ and SiO₂ using ALD layer-by-layer lamination, whichallows the values of x and y be adjusted by the individual cycle numbersof HfO₂ and SiO₂. For example, x may range from 0.02 to 0.05, preferablybetween 0.025 and 0.04, and y may range from 1.8 to 2.2, preferablybetween 1.9 and 2.1. A suitable Hf_(1-x)Si_(x)O_(y) ferroelectricthin-film may be, for example, between 5.0-15.0 nm thick, preferablybetween 8.0-12.0 nm thick for FeFET memory applications. HfO₂ may beprepared from any of the following precursors:tetrakis(ethylmethylamino) hafnium (TEMAH), tetrakis(dimethylamino)hafnium (TDMAH) and hafnium tetrachloride (HfCl₄), using as oxidant O₃or H₂O, at a deposition temperature between 150-400° C. Similarly, SiO₂can be prepared from any of the following precursors:tetrakis(dimethylamino) silane (4DMAS), tris(dimethylamino) silane(3DMAS), tetrakis(ethylmethylamino) silane (TEMA-Si) and silicontetrachloride (SiCl₄), using as oxidant O₃ or H₂O, at a depositiontemperature between 150-400° C.

Zr-doped Hf_(x)Zr_(1-x)O_(y) ferroelectric thin-films may be formed bydepositing HfO₂ and ZrO₂ using ALD layer-by-layer lamination, whichallows the values of x and y be adjusted by the individual cycle numbersof HfO₂ and ZrO₂. For example, x may range between 0.4 and 0.6,preferably between 0.45 and 0.55, and y may range between 1.8 and 2.2,preferably between 1.9 to 2.1. A suitable Hf_(x)Zr_(1-x)O_(y)ferroelectric thin-film may be 5.0-15.0 nm thick, preferably 8.0-12.0 nmthick for FeFET memory applications. HfO₂ may be prepared from any ofthe following precursors: tetrakis(ethylmethylamino) hafnium (TEMAH),tetrakis(dimethylamino) hafnium (TDMAH), and hafnium tetrachloride(HfCl₄), using as oxidant O₃ or H₂O, at a deposition temperature of150-400° C. ZrO₂ may be prepared from any of the following precursors:tetrakis(ethylmethylamino) zirconium (TEMAZ), tetrakis(dimethylamino)zirconium (TDMAZ) and zirconium tetrachloride (ZrCl₄), using as oxidantO₃ or H₂O, at a deposition temperature between 150-400° C.

FIG. 3 a shows a vertical section in the X-Z plane of memory array 300,which includes a regular arrangement of vertical 3-dimensional (3-D)FeFET strings; FIG. 3 a shows, in particular, vertical 3-D FeFET strings300 a, 300 b and 300 c, according to one embodiment of the presentinvention. FIG. 3 a shows three vertical 3-D FeFET strings merely forthe purpose of illustration; memory array 300 may include many more thanvertical 3-D FeFET strings arranged along each of the X- andY-directions.

As shown in FIG. 3 a , each vertical 3-D FeFET string includes (i)multiple annular drain electrodes 301-1, 301-2, ..., and 301-n, (ii)multiple annular source electrodes 302-1, 302-2, ..., and 302-n, (iii)annular channel region 303, (iv) gate or tunnel oxide layer 303 a, and(v) annular ferroelectric layer 304, surrounding common gate electrode308. Common gate electrode 308 may have a conductor core (e.g., tungstenor heavily doped n-type polysilicon) with an outer adhesion layer orbarrier layer (e.g., titanium nitride) 305. Each vertical 3-D FeFETstring is electrically isolated by top and bottom isolation layers 307and 309.

Each drain or source electrode may be provided, for example, by n-typepolysilicon or n-type SiC, titanium nitride, tungsten or any combinationof these materials. Channel region may be provided, for example, byp-type polysilicon or n-type SiC. Ferroelectric layer 304 may beprovided by, zirconium-doped or silicon-doped HfO₂ ferroelectricmaterial. Common gate electrode may be provided, for example, bytungsten/titanium nitride or n⁺ polysilicon/titanium nitride. Gate oxidelayer 303 a may be provided, for example, SiO₂ or SiON.

In each vertical 3-D FeFET string, each memory cell is an MFIStransistor formed by an adjacent pair of drain and source electrodes(e.g., drain electrode 301-1 and source electrode 302-1), and theportions of channel region 303, gate or tunnel oxide layer 303 a,annular ferroelectric-paraelectric layer 304, and common gate electrode308 between the adjacent drain and source electrodes. FIG. 3 a alsoshows that the gate electrodes of vertical 3-D FeFET strings 300 a, 300b and 300 c are electrically connected by conductive global word line306. In memory array 300, (i) the common gate electrodes in a row ofvertical 3-D FeFET strings along the X-direction are electricallyconnected; (ii) drain electrodes at the same vertical level of thevertical 3-D FeFET strings in a row along the Y-direction areelectrically connected; and source electrodes at the same vertical levelof the vertical 3-D FeFET strings in a row along the Y-direction areelectrically connected.

FIG. 3 b shows an Y-Z plane cross section of memory array 300, showingthe gate, drain and source connectivity’s of eight vertical 3-D FeFETstrings, according to one embodiment of the present invention. Again,FIG. 3 b shows eight vertical 3-D FeFET strings merely for the purposeof illustration. In any embodiment, memory array 300 may include morethan eight vertical 3-D FeFET strings arranged along each of the X- andY-directions. FIG. 3 b illustrate selection of MFIS transistor or cell401 by applying selection voltage biases on associated gate electrode308-m, drain electrode 301-m and source electrode 302-m. There are threetypes of non-selected MFIS transistors: (a) “selected gate, non-selecteddrain or source” MFIS transistors— those sharing selected gate electrode308-m, but are associated with one of non-selected drain electrodes 301and one of the non-selected source electrodes 302; (b) “non-selectedgate, selected drain or source” MFIS transistorsthose MFIS transistorsassociated with one of the non-selected gate electrodes 308, butassociated with selected drain electrode 301-m and selected sourceelectrode 302-m; and (c) “non-selected gate, non-selected drain orsource” MFIS transistors - those MFIS transistors associated withneither selected gate electrode 308-m, nor with selected drain electrode301-m and selected source electrode 302-m. In a reading, programming, orerase operation, different voltage biases are required for a selectedMFIS transistor and each of the three types of non-selected MFIStransistors.

FIGS. 4 a-4 l illustrate an exemplary fabrication process for memoryarray 400, in accordance with one embodiment of the present invention.As shown in vertical section in FIG. 4 a , a network of conductors(“global gate lines”), including global gate line 402, are formed oversemiconductor substrate 401, which may be a semiconductor wafer. Theglobal gate lines may be formed out of tungsten, isolated from eachother and from semiconductor substrate 401 by an isolation layer (e.g.,silicon oxide).

Thereafter, as shown in vertical section FIG. 4 b , oxide layer 403(e.g., silicon oxide) and bottom etch stop layer 404 (e.g., n⁺polysilicon) are deposited over the global gate lines. Etch stop layer404 may be patterned, as shown, and embedded in oxide layer 403. Then,as shown in vertical section in FIG. 4 c , alternating layers of siliconoxide layers 405 and silicon nitride layers 406 are deposited, numberedherein as silicon oxide layers 405-1, ..., and 405-n, and siliconnitride layers 406-1, ..., 406-n, respectively.

An array of shafts (“memory holes”) 407 (e.g., memory holes 407-1, 407-2and 407-3) are then etched through the alternating layers of siliconoxide layers 405 and silicon nitride layers 406 down to etch stop layer404, as shown in vertical section in FIG. 4 d(i). FIG. 4 d(ii) shows inhorizontal cross section through one of silicon nitride layers 406,showing memory holes 407-1 to 407-9 of memory array 400 at this step offormation.

Channel layer 409 is then conformally deposited, followed by depositionof thin gate oxide layer 410. Channel layer 409 may be deposited asamorphous silicon and annealed at 850° C. for 2 hours to crystallize.(Alternatively, channel layer 409 may be ALD SiC). Protective layer 408may then be deposited over gate oxide layer 410. A spacer etch is thencarried out to remove any deposited polysilicon and gate oxide from thebottom of memory holes 407. Chemical mechanical polishing (CMP) step maybe carried out to remove materials of protective layer 408, gate oxide410, and channel layer 409 from the top of the structure. The resultingstructure (i.e., memory array 400 at this step of formation) is shown invertical section in FIG. 4 e .

Protective layer 408 is then removed. Ferroelectric layer 411 (e.g., aSi-doped or Zr-doped Hf_(1-x)Si_(x)O_(y), Hf_(x)Zr_(1-x)O_(y)ferroelectric thin-film) is then deposited. CMP and a bottom etch stepremoves excess ferroelectric material from the top of the structure andthe bottom of memory holes 407. The portion of etch stop layer 404exposed at the bottom of memory holes 407 is then removed. An oxide etchthen creates vias that expose the global gate lines (e.g., global gateline 402) underlying memory holes 407. The resulting structure (verticalsection) is shown in FIG. 4 f .

An adhesion/barrier layer of titanium nitride (TiN) 412 is thenconformally deposited. An etch step then removes the TiN material fromthe portion of memory holes 407. Other barrier layers (e.g., tungstennitride or tantalum nitride) may also be used. Memory holes 407 are thenfilled with gate electrode material 413, which may be a chemical vapordeposited tungsten (“CVD W”) or an n⁺ polysilicon (i.e., a heavily dopedn-type polysilicon). Excess deposited material is then removed by CMPfrom the top of the structure. The resulting structure (verticalsection) is shown in FIG. 4 g .

Thereafter, top isolation layer 415 (e.g., silicon nitride) is providedover memory array 400. Top isolation layer 415 is then patterned and anetch step creates slots 414 (e.g., slots 414-1, 414-2, 414-3 and 414-4)through top isolation layer 415 and the alternating silicon nitridelayers 406 and oxide layers 405. The resulting structure (verticalsection) is shown in FIG. 4 h(i). FIG. 4 h(ii) shows a horizontal crosssection of memory array 400 through one of nitride layers 406.

A wet etch step (e.g., hot phosphoric acid) is carried out to remove thesilicon nitride layers 406. During this step, the silicon nitridematerial is removed from the exposed surfaces of silicon nitride layers406 in the sidewalls of slots 414. A further etch step removes exposedportions of channel layer 409 and gate oxide 410. A layer of n⁺semiconductor layer 420 (e.g., n⁺polysilicon or n⁺ SiC) is thendeposited and annealed. TiN layer 418 and tungsten 419 are thendeposited successively to fill the voids left over from removing thesilicon nitride. Excess n⁺ semiconductor, TiN and tungsten materials areremoved from the top of the structure and the sidewalls of slots 414.The resulting structure is shown in vertical and horizontal crosssections in FIGS. 4 i(i) and 4 i(ii), respectively. In FIG. 4 i(i), theresulting structure is magnified in inset where the top two siliconnitride layers 406 (i.e., silicon nitride layers 406-n and 406-(n-1))have been removed. As shown in the inset, in each of the silicon nitridelayer, (a) n⁺ semiconductor layer 420 forms pockets in channel layer 409and gate oxide layer 410 after thermal anneal diffusion, (b) TiN layer418 lines the outside of n⁺ semiconductor layer 420, and (c) tungstenlayer 419 fills the remainder of the voids. The pockets of n⁺semiconductor layer 420 become drain and source regions of an MFIStransistor. TiN layers 418 and tungsten layers 419 become source ordrain electrodes 423.

In some embodiments, silicon nitride layers 406 is not completelyremoved. As etching of silicon nitride layers 406 proceeds from thesidewalls of slots 414, so that a strip of silicon nitride divides andelectrically the resulting source or drain terminals isolates onopposite sides of each memory hole. In this manner, each memory hole nowprovides two vertical 3-D FeFET strings, as the n⁺ semiconductor pocketson opposite sides of each silicon nitride layer of each memory hole formseparate drain or source regions. This alternative embodiment isillustrated in the structure is shown in vertical and horizontal crosssections in FIGS. 4 j(i) and 4 j(ii), respectively. As shown in FIG. 4j(ii), silicon nitride layers 421, which is left over from theincomplete removal of silicon nitride layers 406 provide separate sets423L and 423R of drain or source electrodes.

Silicon oxide 422 is then deposited to fill slots 414. A CMP stepremoves excess silicon oxide from the top of memory array 400. Theresulting structure in vertical and horizontal cross sections are shownin FIGS. 4 k(i) and 4 k(ii), respectively, for the embodiment of FIGS. 4i(i) and 4 i(ii). Likewise, the resulting structure in vertical andhorizontal cross sections are shown in FIGS. 41(i) and 41(ii),respectively, for the embodiment of FIGS. 4 j(i) and 4 j(ii).

Connections to the drain or source electrodes 423 (or 423L and 423R, inthe alternative embodiment) can be made using the staircaseconfiguration used in 3-D NAND non-volatile memory arrays. FIG. 5 showsmemory array 400 provided electrical contacts or connections to drain orsource electrodes 423 via staircase structures on both sides of memoryarray 400 and contacts or connections to gate electrodes 413 using thebottom global gates (e.g., global gate 402). The staircase configurationand associated fabrication methods are known to those of ordinary skillin the art.

In one embodiment, the polarization switching voltages are ± 1.5 voltsacross the ferroelectric capacitor layer of the MFIS, for “1” and “0”states, respectively. During a programming or an erase operation, thevoltage across the ferroelectric layer is roughly half of thegate-to-source voltage (V_(GS)) of the MFIS. Thus, programming of theMFIS may be achieved using a programming voltage V_(PGM) 0f 6-7 volts atthe gate electrode. Table 1 shows the voltage biases for MFIStransistors in memory array 400 during a programming operation:

Table 1 MFIS TYPE Gate Voltage Drain Voltage Source Voltage Selectedcell V_(PGM) 0.0 0.0 Selected Gate, non-selected source or drain V_(PGM)2/3 V_(PGM) ⅔ V_(PGM) Non-selected gate, selected drain or source ⅓V_(PGM) 0.0 0.0 Non-selected gate, non-selected drain or source ⅓V_(PGM) ⅔ V_(PGM) ⅔ V_(PGM)

As shown in Table 1, program disturb is avoided in the non-selected MFIStransistors because in each case, the magnitude of half gate-to-sourcevoltage (V_(GS)) is less than ⅓ V_(PGM), which is by design less thanthe polarization switching voltage for state “0”.

Similarly, an erase operation on an MFIS transistor may be achievedusing an erase voltage V_(ERA) of 6-7 volts at the gate electrode. Table2 shows the voltage biases for MFIS transistors in memory array 400during an erase operation:

Table 2 MFIS TYPE Gate Voltage Drain Voltage Source Voltage Selectedcell 0.0 V_(ERA) V_(ERA) Selected Gate, non-selected source or drain 0.0⅟3 V_(ERA) ⅓ V_(ERA) Non-selected gate, selected drain or source ⅔V_(ERA) V_(ERA) V_(ERA) Non-selected gate, non-selected drain or source⅔ V_(ERA) V_(ERA) V_(ERA)

As shown Table 2, erase disturb is avoided in the non-selected MFIStransistors because in each case, the magnitude of half thegate-to-source voltage (V_(GS)) are less than ⅓ V_(ERA), which is bydesign less than the polarization switching voltage for state “1”.

A read operation may be achieved using a read voltage V_(READ) of0.0-0.5 volts at the gate electrode and drain voltage V_(DD) at 0.5-2.0volts. Table 3 shows the voltage biases for MFIS transistors in memoryarray 400 during a read operation:

Table 3 MFIS TYPE Gate Voltage Drain Voltage Source Voltage Selectedcell V_(READ) V_(DD) 0.0 Selected Gate, non-selected source or drainV_(READ) 0.0 0.0 Non-selected gate, selected drain or source 0.0 ornegative V_(DD) 0 Non-selected gate, non-selected drain or source 0.0 ornegative 0.0 0.0

As shown Table 3, MFIS transistors not on the same word line (i.e.,non-selected gate electrodes) are provided a gate voltage of 0.0 voltsor less, which results in a very low current drawn in these transistors.

FIGS. 6 a-6 j illustrate an exemplary fabrication process for memoryarray 600, in accordance with one embodiment of the present invention.Unlike memory array 400, the gate electrodes of the MFIS transistors inmemory array 600 are not connected by a network of global gate linesformed underneath the memory array. Instead, as shown in verticalsection FIG. 6 a , oxide layer 603 (e.g., silicon oxide) and bottom etchstop layer 604 (e.g., silicon nitride) are deposited in succession overa planar surface of semiconductor substrate 601. Etch stop layer 604 maybe patterned, as shown, and embedded in oxide layer 603. Then, as shownin vertical section in FIG. 6 b , alternating layers of silicon oxidelayers 605 and silicon nitride layers 606 are deposited, numbered hereinas silicon oxide layers 605-1, ..., and 605-n, and silicon nitridelayers 606-1, ..., 606-n, respectively. An array of memory holes 607(e.g., memory holes 607-1, 607-2 and 607-3) are then etched through thealternating layers of silicon oxide layers 605 and silicon nitridelayers 606 down to etch stop layer 604, as shown in vertical section inFIG. 6 c(i). FIG. 6 c(ii) shows in horizontal cross section through oneof silicon nitride layers 606, showing memory holes 607-1 to 607-9 ofmemory array 600 at this step of formation.

Channel layer 609 is then conformally deposited, followed by depositionof thin gate oxide layer 610. Channel layer 609 may be deposited asamorphous silicon and annealed at 850° C. for 2 hours to crystallize.Alternatively, channel layer 609 may be provided by ALD SiC.Ferroelectric layer 611 (e.g., a Si-doped or Zr-dopedHf_(1-x)Si_(x)O_(y) , Hf_(x)Zr_(1-x)O_(y) ferroelectric thin-film) isthen deposited. The resulting structure (vertical section) is shown inFIG. 6 d .

An adhesion/barrier layer of titanium nitride (TiN) 612 is thenconformally deposited. Memory holes 607 are then filled with gateelectrode material 613, which may be a CVD W or an n⁺polysilicon. A CMPstep removes excess gate oxide material 613 from the top of memory array600. The resulting structure (vertical section) is shown in FIG. 6 e .

Thereafter, top isolation layer 615 (e.g., silicon nitride) is providedover memory array 600. Top isolation layer 615 is then patterned and anetch step creates slots 614 (e.g., slots 614-1, 614-2, 614-3 and 614-4)through top isolation layer 615, TiN layer 612, ferroelectric layer 611,gate oxide layer 610, channel layer 609 and the alternating siliconnitride layers 606 and oxide layers 605. The resulting structure(vertical section) is shown in FIG. 6 f(i). FIG. 6 f(ii) shows ahorizontal cross section of memory array 600 through one of nitridelayers 606.

An etch step (hot phosphoric acid) is carried out to remove the siliconnitride layers 606. During this step, the silicon nitride material isremoved from the exposed surfaces of silicon nitride layers 606 in thesidewalls of slots 614. A further etch step removes exposed portions ofchannel 609 and gate oxide 610. A layer of n⁺ semiconductor layer 620(e.g., n⁺ polysilicon or n⁺ SiC) is then deposited and annealed. TiNlayer 618 and tungsten 619 are then deposited successively to fill thevoids left over from removing the silicon nitride. Excess n⁺semiconductor, TiN and tungsten materials are removed from the top ofthe structure and the sidewalls of slots 614, in substantially. Thesesteps are provided in substantially the same manner as discussed abovewith respect to vertical and horizontal cross sections in FIGS. 4 i(i)and 4 i(ii), respectively. The pockets of n⁺ semiconductor layer 620become drain and source regions of an MFIS transistor. TiN layers 618and tungsten layers 619 become source or drain electrodes 623. Siliconoxide 622 is then deposited to fill slots 614. A CMP step removes excesssilicon oxide from the top of memory array 600. The resulting structurein vertical and horizontal cross sections are shown in FIGS. 6 g(i) and6 g(ii), respectively,

As discussed above with respect to FIGS. 4 j(i) and 4 j(ii), in someembodiments, silicon nitride layers 606 is not completely removed. Asetching of silicon nitride layers 606 proceeds from the sidewalls ofslots 614, so that a strip of silicon nitride divides and electricallythe resulting source or drain terminals isolates on opposite sides ofeach memory hole. In this manner, each memory hole now provides twovertical 3-D FeFET strings, as the n⁺ semiconductor pockets on oppositesides of each silicon nitride layer of each memory hole form separatedrain or source regions. This alternative embodiment is illustrated inthe structure is shown in vertical and horizontal cross sections inFIGS. 6 h(i) and 6 h(ii), respectively. As shown in FIG. 6 h(ii),silicon nitride layers 621, which is left over from the incompleteremoval of silicon nitride layers 606 provide separate sets 623L and623R of drain or source electrodes.

Silicon oxide layer 618 is deposited over top isolation layer 615,filling any gap on memory array 600 and planarized by a CMP step.Thereafter, silicon oxide layer 618 is patterned. An etch step createsvia through silicon oxide layer 618 and top isolation layer 615 toexpose gate electrode material 613. Metallic conductor (e.g., TiN andtungsten plug) 616 is then provided to fill the vias. A CMP stepplanarizes the surface of memory array 600. The resulting structure isshown in vertical section in FIG. 6 i . Thereafter, top global gates(e.g., global gate 617) are provided above silicon oxide layer 618 toelectrically connect gate electrodes 613 through the conductor- filledvias, as shown in FIG. 6 j .

FIGS. 7 a-7 g illustrate an exemplary fabrication process for memoryarray 700, in accordance with one embodiment of the present invention.Unlike the MFIS transistors of memory arrays 400 and 600 discussedabove, an MFIS transistor of memory array 700 includes an additionalcharge-storage layer between the gate oxide layer and the ferroelectriclayer.

FIG. 7 a shows memory array 700 after (i) a network of global gate lines(e.g., tungsten), including global gate line 702, are formed oversemiconductor substrate 701, which may be a semiconductor wafer; and(ii) oxide layer 703 (e.g., silicon oxide) and bottom etch stop layer704 (e.g., n⁺ polysilicon) are deposited over the global gate lines; and(iii) alternating layers of silicon oxide layers 705 and n⁺semiconductor (e.g., n⁺ polysilicon or n⁺ SiC) 706 are deposited,numbered herein as silicon oxide layers 705-1, ..., and 705-n, and n⁺polysilicon layers 706-1, ..., 706-n, respectively. The structure ofFIG. 7 a may be formed using substantially the same steps as thosedescribed above with respect to FIGS. 4 a-4 c , except conductive n⁺semiconductor material replaces silicon nitride in the alternatinglayers. Using n⁺ polysilicon or n⁺ SiC is an option for drain and sourceelectrodes, although n⁺ semiconductor materials have a higherresistivity than metal. However, if metal is selected for drain andsource electrodes, a metal replacement step (see, e.g., FIGS. 4 i and 4j for memory array 400 and FIGS. 6 f and 6 g for memory array 600) maybe required.

Slots 714 may be created at this time, instead of after the MFIStransistors have been substantially formed (see, e.g., FIGS. 4 h(i) and6 f(i), which creating slots 414 of memory array 400 and slots 614 ofmemory array 600), because the metal replacement step is not necessary.(The metal replacement steps access the silicon nitride layers throughthe slots.) Slots 714, which divide memory array 700 into sections 708,may then be filled with oxide, as shown in vertical and horizontalsections in FIGS. 7 b(i) and 7 b(ii).

Memory holes 707 (e.g., memory holes 407-1, 407-2 and 407-3) are thenetched through the alternating layers of silicon oxide layers 705 and n⁺polysilicon layers 706 down to etch stop layer 704, as shown in verticalsection in FIG. 7 c(i). FIG. 7 c(ii) shows in horizontal cross sectionthrough one of n⁺ polysilicon layers 706, showing memory holes 707-1 to707-9 of memory array 700 at this step of formation.

Channel layer 709 is then conformally deposited, followed by depositionof thin gate oxide layer 710. Channel layer 709 may be deposited asamorphous silicon and annealed at 850° C. for 2 hours to crystallize.Alternatively, channel layer 709 may be provided by ALD SiC. Protectivelayer 708 may then be deposited over gate oxide layer 710. A spacer etchis then carried out to remove any deposited polysilicon and gate oxidefrom the bottom of memory holes 707. A CMP step may be carried out toremove materials of protective layer 708, gate oxide 710, and channellayer 709 from the top of the structure. The resulting structure (i.e.,memory array 700 at this step of formation) is shown in vertical sectionin FIG. 7 d .

Protective layer 708 is then removed. Thereafter, charge- trapping layer733 is conformally deposited. An anisotropic etch then removes thecharge-trapping material at the bottom of memory holes 707 to expose theunderlying etch stop layer 704. The exposed portions of etch stop layer704 and the portions of oxide layer 703 are removed in successiveetching steps to create vias that expose the global gate linesunderneath. The resulting structure is shown in vertical section in FIG.7 e .

Ferroelectric layer 711 (e.g., a Si-doped or Zr-dopedHf_(1-x)Si_(x)O_(y), Hf_(1-x)Zr_(x)O_(y) ferroelectric thin-film) isthen deposited. CMP and a bottom etch step removes excess ferroelectricmaterial from the top of the structure and the bottom of memory holes707. An adhesion/barrier layer of titanium nitride (TiN) 712 is thenconformally deposited. An etch step then removes the TiN material fromthe portion of memory holes 707. Memory holes 707 are then filled withgate electrode material 713, which may be a CVD W or an n⁺ polysilicon.Excess deposited material is then removed by CMP from the top of thestructure. The resulting structure (vertical section) is shown in FIG. 7f .

Thereafter, top isolation layer 715 (e.g., silicon nitride) is providedover memory array 700. The resulting structure (vertical section) isshown in FIG. 7 g .

FIGS. 8 a-8 j illustrate an exemplary fabrication process for memoryarray 800, in accordance with one embodiment of the present invention.Unlike the MFIS transistors of memory arrays 400, 600 and 700 discussedabove, an MFIS transistor of memory array 800 has a unit cell in whichthe source and drain lines are fabricated out of the same layer ofsemiconductor material.

FIG. 8 a shows memory array 800 after (i) a network of global gate lines(e.g., tungsten), including global gate line 802, are formed oversemiconductor substrate 801, which may be a semiconductor wafer; and(ii) oxide layer 803 (e.g., silicon oxide) and bottom etch stop layer804 (e.g., n⁺ polysilicon) are deposited over the global gate lines; and(iii) alternating layers of silicon oxide layers 805 and silicon nitridelayers 806 are deposited, numbered herein as silicon oxide layers 805-1,..., and 805-n, and silicon nitride layers 806-1, ..., 806-n,respectively. (In FIG. 8 a , semiconductor substrate 801 and global gatelayer 802 are omitted; semiconductor substrate 801 and global gate layer802 have substantially the same structure, and are formed insubstantially the same manner, as semiconductor substrate 701 and globalgate layer 702 discussed above.) The structure of FIG. 8 a may be formedusing substantially the same steps as those described above with respectto FIGS. 4 a-4 c

Memory holes 807 (e.g., memory holes 407-1, 407-2 and 407-3) are thenetched through the alternating layers of silicon oxide layers 805 andsilicon nitride layers 806 down to etch stop layer 804, as shown invertical section in FIG. 8 b(i). FIG. 8 b(ii) shows in horizontal crosssection through one of silicon nitride layers 706, showing memory holes807-1 to 807-9 of memory array 800 at this step of formation.

Thereafter, a silicon nitride recess etch using, for example, hotphosphoric acid, is performed to recess silicon nitride layers 806 fromexposed sidewalls of memory holes 807, as shown in FIG. 8 c . Channellayer 809 (e.g., p⁻—type polysilicon or p⁻- type SiC) is then depositedto fill the recesses created by the silicon nitride recess etch. Ananisotropic etch step removes the excess channel material from memoryholes 809, including the sidewalls, exposing etch stop layer 804. Excesschannel material may also be removed from top oxide layer 805-n. Theresulting structure is shown in FIG. 8 d(i). FIG. 8 d(ii) shows ahorizontal section through one of silicon nitride layers 806. Channellayer 709 may be deposited as amorphous silicon or SiC and annealed tocrystallize.

Thin gate oxide layer 810 and ferroelectric layer 811 (e.g., a Si-dopedor Zr-doped Hf_(1-x)Si_(x)O_(y), Hf_(1-x)Zr_(x)O_(y) ferroelectricthin-film) are then conformally deposited into memory holes 807. A CMPstep removes excess gate oxide and ferroelectric materials from the topof the structure. An adhesion/barrier layer of titanium nitride (TiN)812 is then conformally deposited. The resulting structure is shown inFIG. 8 e .

Gate electrode material 813, which may be a CVD W or an n⁺ polysilicon,is then deposited to fill the remainder of memory holes 807. Excessdeposited gate electrode and TiN materials are then removed by CMP fromthe top of memory array 800. The resulting structure (vertical section)is shown in FIG. 8 f . Thereafter, top isolation layer 815 (e.g.,silicon nitride) is provided over memory array 800. Slots 814 are thencut. The resulting structure is shown in FIG. 8 g(i). A horizontalstructure through one of the silicon nitride-channel layers is shown inFIG. 8 g(ii).

A hot phosphoric acid etch recesses silicon nitride layers 806 from thesidewalls of slots 814, as shown in FIG. 8 h(i). A horizontal structurethrough one of the silicon nitride-channel layers is shown in FIG. 8g(ii). Thereafter, n⁺ semiconductor layer (e.g., n⁺ polysilicon or n⁺SiC) 818 is deposited by diffusion conformally to line the layers ofpockets from recessing silicon nitride layers 805. If necessary, ananneal step provides crystallization and activates the dopants.Thereafter, the remaining of the layers of pockets are lined by adhesivelayer 817 (e.g., TiN) and filled by tungsten layer 819. Excess TiN,tungsten and n⁺ semiconductor materials are then removed from thesidewalls and at the bottoms of slots 814 and from the top of structure.The n⁺ semiconductor pockets in each slot is designated to become eithersource regions 821 or drain regions 822, with adjacent slots beingassigned the opposite types. The resulting structure is shown in FIG. 8i(i). A horizontal structure through one of the pocket layers is shownin FIG. 8 i(ii). Portion 820 of the structure of FIG. 8 i(i)is enlargedin FIG. 8 i(iii).

Slots 814 are then filled with by insulator 825 (e.g., a silicon oxide),which also provided as a top gap fill layer. After planarization usingCMP, gate line contacts 826 are through top gap fill layer 825 and topisolation layer 813. One or more layers 827 of conductors (“gate lines”)may be provided to electrically connect gate line contacts 826. Theresulting structure is shown in FIG. 8 j .

The detailed description above describes alternative embodiments inwhich SiC is provided in source, drain and channel regions of an FeFET.These FeFETs (“SiC FeFETs”) have very low leakage currents, resulting inhigher endurance than its polysilicon counterparts (e.g., 10⁹ or higherin SiC FeFETs, versus 10⁵ in comparable polysilicon-based FeFETs). Also,because of the low intrinsic carrier concentration between 10⁻⁷ cm⁻³(4H)and 10⁻⁵ cm⁻³(6H), data retention time in SiC FeFETs is considerablyhigher (e.g., 10⁶ years). In one implementation, an SiC FeFET has dataretention of 10 year operating at 150° C. In comparison, a comparablesilicon channel FeFET has comparable data retention operating at a muchlower operating temperature of 80° C. In fact, SiC FeFET can operate at200° C. or higher. A SiC FeFET also has the advantage of higherswitching frequencies due to its larger saturation drift velocity. Forexample, 4H SiC has a saturation drift velocity that is 2.7 timesgreater than silicon.

The above detailed description is provided to illustrate specificembodiments of the present invention and is not intended to be limiting.Numerous variations and modifications within the scope of the presentinvention are possible. For example, with respect to FIGS. 7 a-7 g , thelocations of ferroelectric layer 711 and charge-trapping layer 733 canbe swapped, and an additional blocking oxide layer can be insertedbetween titanium nitride layer 712 and ferroelectric layer 711. Thepresent invention is set forth in the accompanying drawings.

I claim:
 1. A memory string formed above a planar surface of substrate,comprising: a gate electrode extending lengthwise along a firstdirection substantially orthogonal to the planar surface, aferroelectric layer provided over at least a portion of the gateelectrode along a second direction orthogonal to the first direction andextending lengthwise along the first direction; a gate oxide layerprovided over at least a portion of the ferroelectric layer along thesecond direction and extending lengthwise along the first direction; aplurality of semiconductor structure provided along the first directionadjacent the gate oxide layer, wherein each semiconductor structurecomprises (i) a first semiconductor material of a first conductivitytype; and (ii) second and third semiconductor materials electricallybeing isolated from each other and each being coplanar with and adjacentthe first semiconductor material, the second and third semiconductormaterials each being of a second conductivity type different from thefirst conductivity type, (iii) wherein at least one of the first, thesecond and the third semiconductor materials comprise silicon carbide(SiC), (iv) wherein the gate electrode, the ferroelectric layer, thegate oxide layer and the semiconductor structure form a storagetransistor of the memory string, and (v) wherein the first, second andthird semiconductor materials form the channel, source and drain regionsof the storage transistor.
 2. The memory string of claim 1, wherein thefirst semiconductor material comprises p-type atomic layer depositedsilicon carbide.
 3. The memory string of claim 1, wherein at least oneof the second and the third semiconductor materials comprises n⁺-typechemical vapor deposited silicon carbide.
 4. The memory string of claim1, further comprising a barrier layer provided between the gateelectrode and the ferroelectric layer.
 5. The memory string of claim 4,wherein the barrier layer comprises titanium nitride, tungsten nitrideor tantalum nitride.
 6. The memory string of claim 1, wherein the gateelectrode comprises tungsten or a heavily doped semiconductor.
 7. Thememory string of claim 1, further comprising a conductor adjacent toeach of the second and third semiconductor materials of eachsemiconductor structure.
 8. The memory string of claim 7, wherein theconductor comprises tungsten, a metallic adhesive layer, or acombination thereof.
 9. The memory string of claim 7, wherein the drainor source region each comprise n⁺ polysilicon.
 10. The memory string ofclaim 1, wherein the memory string is one of a plurality of memorystrings in a memory array, wherein the memory array comprises astaircase configuration providing electrical contacts to each of thesource or drain electrodes.
 11. The memory string of claim 1, whereinthe memory string is one of a plurality of memory strings in a memoryarray, wherein the memory array comprises a network of global word lineconductors each connecting the gate electrodes of a selected group ofthe memory strings.
 12. The memory string of claim 11, wherein thenetwork of global word line conductors is provided above the memorystrings.
 13. The memory string of claim 1, wherein the ferroelectriclayer comprises a HfO₂ ferroelectric material.
 14. The memory string ofclaim 13, wherein the ferroelectric layer is 5.0-30.0 nm thick,preferably 8.0-20.0 nm thick.
 15. The memory string of claim 13, whereinthe ferroelectric layer comprises a zirconium-doped hafnium siliconoxide.
 16. The memory string of claim 15, wherein the zirconium-dopedhafnium silicon oxide has a zirconium content of 40-60%, preferably45-55%.
 17. The memory string of claim 15, wherein the zirconium-dopedhafnium silicon oxide comprises Hf_(x)Zr_(1-x)O_(y) ferroelectricthin-films, where x ranges between 0.4 and 0.6, preferably between 0.45and 0.55, and y ranges between 1.8 and 2.2, preferably between 1.9 to2.1.
 18. The memory string of claim 15, wherein the zirconium-dopedhafnium silicon oxide is prepared by depositing HfO₂ and ZrO₂using anALD layer-by-layer lamination step.
 19. The memory string of claim 13,wherein the ferroelectric layer comprises a silicon-doped hafniumsilicon oxide.
 20. The memory string of claim 19, wherein thesilicon-doped hafnium silicon oxide has a silicon content of 2.0-5.0%,preferably 2.5-4.5%.
 21. The memory string of claim 19, wherein thesilicon-doped hafnium silicon oxide comprises Hf_(x)Si_(1-x)O_(y)ferroelectric thin-films, where x ranges from 0.02 to 0.05, preferablybetween 0.025 and 0.04, and y ranges from 1.8 to 2.2, preferably between1.9 and 2.1.
 22. The memory string of claim 19, wherein thesilicon-doped hafnium silicon oxide is prepared by depositing HfO₂ andSiO₂ using an ALD layer-by-layer lamination step.
 23. The memory stringof claim 20, further comprising a charge-trapping layer between the gateoxide layer and the ferroelectric layer or between the ferroelectriclayer and a barrier layer adjacent the gate electrode.
 24. The memorystring of claim 1, wherein the barrier layer comprises titanium nitride.